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(R)
AN1061 APPLICATION NOTE
Designing with L4978, 2A High Efficiency DC-DC Converter
by N. Tricomi and D. Arrigo
INTRODUCTION The L4978 is a 2A monolithic dc-dc converter, step- down , operating at fix frequency continuous mode. It is realised in BCD60 II technology,and it's available in two plastic packages, MINIDIP and SO16L. One direct fixed output voltage at 3.3V 1% is available, adjustable for higher output voltage values, till 40V, by an external voltage divider. The operating input supply voltage ranges from 8V to 55V, while the absolute value, with no load, is 60V. New internal design solutions and superior technology performance allow to generate a device with improved efficiency in all the operating conditions and with reduced EMI due to an innovative internal driving circuit, and reduced external component counts. While internal limiting current and thermal shutdown are today considered standard protection functions, mandatory for a safe load supply, oscillator with voltage feedforward improves line regulation and overall control loop. Soft-start avoids output overvoltages at turn-on, while, shorting this pin to ground, the device is completely disabled, going into zero consumption state.
September 2000
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AN1061 APPLICATION NOTE
DEVICE DESCRIPTION For a better understanding of the device and its working principles, a short description of the main building blocks is given here below, with packaging options and complete block diagram. Figure 1 shows the two packaging options, with the pin function assignments. Figure 1. Pins connection.
N.C. GND
1 2 3 4 5 6 7 8
D97IN596
16 15 14 13 12 11 10 9
N.C. N.C. FB COMP BOOT VCC N.C. N.C.
GND SS_INH OSC OUT
1 2 3 4
D97IN595
8 7 6 5
FB COMP BOOT VCC
SS_INH OSC OUT OUT N.C. N.C.
Figure 2. Block diagram.
VCC 5 THERMAL SHUTDOWN VOLTAGES MONITOR CBOOT CHARGE SS_INH 7 6 8 E/A PWM BOOT 2 INHIBIT SOFTSTART 3.3V COMP FB INTERNAL REFERENCE INTERNAL SUPPLY 5.1V
R S
3.3V
Q DRIVE
OSCILLATOR 1 GND
CBOOT CHARGE AT LIGHT LOADS
3 OSC
4 OUT
D97IN594
Power supply & Voltage reference The device is provided with an internal stabilised power supply (of about 12V typ. ) that powers the analog and digital control blocks and the bootstrap section. From this preregulator, a 3.3V reference voltage 2%, is internally available.
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AN1061 APPLICATION NOTE
Oscillator and voltage feedforward. Just one pin is necessary to implement the oscillator function, with inherent voltage feedforward. Figure 3. Oscillator internal circuit.
VCC ROSC TO PWM COMPARATOR Osc 5R + CLOCK
Q1 COSC
R
Q2
1V
D97IN655A
A resistor Rosc and a capacitor Cosc connected as shown in Figure 3, allow the setting of the desired switching frequency in agreement with the below formula: FSW = 1 6 Rosc Cosc ln + 100 Cosc 5
Where Fsw is in kHz, Rosc in K and Cosc in nF. The oscillator capacitor, Cosc , is discharged by an internal mos transistor with 100 of Rdson (Q1) and during this period the internal threshold is set at 1V by a second mos, Q2 . When the oscillator voltage capacitor reaches the 1V threshold, the output comparator turns off the mos Q1 and turns on the mos Q2, restarting the Cosc charge. Figure 4. Switching frequency vs. Rosc The oscillator block, shown in figure 4, generates a sawand Cosc. tooth wave signal that sets the switching frequency of the fsw D97IN630 system. (KHz) This signal, compared with the output of the error ampliTamb=25C 500 fier, generates the PWM signal that will modulate the conduction time of the power output stage. 0.8 2nF 200 The way the oscillator has been integrated,does not re1.2 nF quire additional external components to benefit of the 100 voltage feedforward function. 2.2 nF The oscillator peak-to-valley voltage is proportional to the 50 3.3n F supply voltage, and the voltage feedforward is operative 4.7n from 8V to 55V of input supply. F 20 5.6n F VCC -1 Vosc = 10 6 5 Also the V/t of the sawtooth is directly proportional to 0 20 40 60 80 R2(K) the supply voltage. As Vcc increases, the Ton time of the power transistor decreases in such a way to provide to the chocke, and finally also the load, the product Voltxsec constant. Figure 5 shows how the duty cycle varies as a result of the change on the V/t of the sawtooth with the Vcc.
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AN1061 APPLICATION NOTE
Figure 5. Voltage Feedforward Function. The output of the error amplifier doesn't change in order to maintain the output voltage constant and in regulation. With this function on board, the output response time is greatly reduced in presence of an abrupt change on the supply voltage, and the output ripple voltage at the mains frequency is greatly reduced too. In fact, the slope of the ramp is modulated by the input ripple voltage, generally present in the order of some tens of Volt, for both off-line and dc-dc converters using mains transformers. The charge and discharge time are approximable to: 6 Tch = Rosc Cosc ln( )
V1
Vi=30V Vi=15V Vc t
V2-3 Vi=30V Vi=15V
t
D97IN684
5
Figure 6. Maximum Duty Cycle vs Rosc and Cosc as parameter
Dmax
5.3nF
Tdis = 100 Cosc The maximum duty cycle is a function of Tch, Tdis and an internal delay and is expressed by the equation: Dmax = Rosc Cosc ln( ) - 80 109
D97IN685
4.7nF
0.90
2.2nF 1.2nF 0.8nF
6 5
0.80
6 Rosc Cosc ln( ) + 100 Cosc 5 and is represented in figure 6.
Current Protection The L4978 has two current limit levels, pulse by pulse and hiccup modes. 0.60 Increasing the output current till the pulse by pulse 0 4 8 12 16 20 24 28 32 ROSC(K) limiting current threshold (Ith1 typ. value of 3A) the controller reduces the on-time till the value of TB = 300ns that is a blanking time in which the current limit protection does not trigger. This minimun time is necessary to avoid undesirable intervention of the protection due to the spike current generated during the recovery time of the freewheeling diode. In this condition, because of this fixed balnking time, the output current is given by: Imax = [VCC TB F sw - Vf (1 - TB Fsw)] [Ro + (RD + RL) (1 - TB Fsw) + (Rdson + RL)TB Fsw ]
0.70
Where Ro is the load resistance, Vf is the diode forward voltage. RD and RL are the series resistance of, respectively, the freewheeling diode and the choke. Typical output characteristics are represented in figure 7.1 and 7.2. In fig 7.1, the pulse by pulse protection is sufficient to limit the current. In fig 7.2 the pulse by pulse protection is no more effective to limit the current due to the minimun Ton fixed by the blanking time TB, and the hiccup protection intervenes because the output peak current reachs the relative threshold. At the pulse by pulse intervention (point A) the output voltage drops because of the Ton reduction, and the current is almost constant. Going versus the short circuit condition, the current is only limited by the series resistances RD and RL (see relation above) and could reach the hiccup threshold (point B), set 20% higher than the pulse by pulse. Once the hiccup limiting current is operating, in output short circuit
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AN1061 APPLICATION NOTE
condition, the delivered average output current decreases dramatically at very low values (point C). Figure 7.1. Output Characteristic
VO
Figure 7. 2. Output Characteristic
VO
A
A
B C
D98IN909A
3A
3.6A
IO
D99IN1077
3A 3.6A
IO
Figure 8. Current Limit internal schematic circuit.
OSC S R VTh1 VTh2 + + Q VCC
OUT PWM + OSC THERMAL UNDERVOLTAGE + HICCUP SOFT START LATCH S R Q 12V
VFB VREF +
D97IN658
0.4
CSS
-
Figure 8 shows the internal current limiting circuitry. Vth1 is the pulse by pulse while Vth2 is the hiccup threshold. The sense resistor is in series with a small mos realised as a partition of the main DMOS. The Vth2 comparator (20% higher than Vth1) sets the soft start latch, initialising the discharge of the soft start capacitor with a constant current (about 22A). Reaching about 0.4V, the valley comparator resets the soft start latch, restarting a new recharge cycle. Figure 9 Shows the typical waveforms of the current in the output inductor and the soft start voltage (pin 2). During the recharging of the soft start capacitor, the Ton increases gradually and, if the short circuit is still present, when Ton>TB and the output peak current reachs the threshold, the hiccup protection intervenes again. So, the value of the soft start capacitor must not be too high (in this case the Ton increases slowly thus taking much time to reach the TB value) to avoid that during the soft start slope the current exceeds the limit before the protection activation. The folllowing diagrams of Figure 10a and Figure 10b show the maximum allowed soft-start capacitor as a function of the input voltage, inductor value and switching frequency. A minimun value of the soft start capacitance is necessary to guarantee, in short circuit condition, the functionality of the limiting current circuitry. Infact, with a capacitor too small, the frequency of the current peaks (see figure 9) is high and the mean current value in short circuit increases.
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AN1061 APPLICATION NOTE
Figure 9. Output current and soft-start voltage
Figure 10a. Maximum Soft Start Capacitance with fSW = 100kHz
L (H)
fsw=100KHz
D97IN745
680nF 470nF
400
330nF
300
200
220nF
100
100nF
0 15 20 25 30 35 40 45 50 VCCmax(V)
Figure 10b. Maximum Soft Start Capacitance with fsw = 200kHz
L (H)
D97IN746
fsw=200KHz
56nF
300
47nF
200
33nF
22nF
100
0 15 20 25 30 35 40 45 50 VCCmax(V)
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AN1061 APPLICATION NOTE
Soft Start and Inhibit functions. The soft start and the inhibit functions are realised using one pin only, pin2. Soft-start is requested to inizialise all internal functions with a correct start-up of the system without overstressing the power stage, avoiding the intervention of the current protection, and having an output voltage rising smoothly without output overshoots. At Vcc Turn-on or having had an intervention of inhibit function, an initial 5A internal current generator starts to charge the soft-start capacitor, from 0V to about 1.8V. From this hysteretic threshold, a 40A current generator is activated, putting in off state the previous generator. At this point, the output PWM starts, initiating the rising phase of the output voltage. The soft-start capacitor is quickly discharged in case of: * Thermal protection intervention * Hiccup limiting current condition * Supply voltage lower than UVLO off threshold. The soft-start and inhibit schematic diagram is shown in figure 11. Figure 11. Soft-Start and inhibit functions Internal Circuit .
12V
40A
5A Comp1
1.2V 1.8V
S1
+ SS_INH 1K CSS
D97IN808A
S4
UNDERVOLTAGE PROT. HICCUP PROT. THERMAL PROT. S R Q
S2
S3
10A Comp2 + 1.3V
At device turn-on, the soft-start capacitor has no charge, with 0V at its terminals. From 0V to 1.8V, switch S3 is opened and S4 is closed. Soft-start capacitor is charged with 5A. At 1.8V, comp1 change the output status, opening S4 and closing S3, and the device starts to generate the PWM signal, rising smothly the output voltage. Till this moment, S2 is opened, S1 closed. By closing S3, the soft-start capacitor is charged with 40A reaching its saturation voltage. This procedure is repeated at each Vcc turn-on. Turning Vcc off, the soft-start capacitor is discharged with a constant 10A (S2 closed, S3 closed, S1 and S4 open), from the moment when Vcc is crossing the UVLO off threshold. The final discharge value is 1.2V. In case of the Css is discharged using an external grounded element when the voltage at Css reaches the threshold of 1.3V Comp2 resets the flip flop, S1 is closed, S2 is opened and the 40A current generator is activated. The external switch, sinking some mA, discharges the soft-start under the 1.2V Comp1 threshold, opening S3 and closing S4. At this point the device is in disable, sourcing only 5A through pin 2. When the external grounding element is removed, the device restarts charging the soft start capaci7/19
AN1061 APPLICATION NOTE
tance, initially, with 5A till the voltage reaches the 1.8V threshold and Comp1 connects the 40A charging current generator. In case of thermal shutdown or overcurrent protection intervention the power is turned off and the flip flop turns off S2 and turns on S1. The soft-start is discharged till the voltage reaches the 1.3V threshold, and Comp2 resets the flip flop. S1 is closed, S2 is opened and the soft-start capacitance is charged again. Figure 11a shows the systems signals during Inhibit, overcurrent and Vcc turn off. t1 and t2 can be calculated by the following equations: Vo t1 = 0.36 Css; t2 = Css Ich 6 Dmax where Dmax is 0.95, Css is in F and Ich is in A . Soft-start time (t2) versus output voltage and Css is shown in Figure 12.
Thanks to the voltage feedforward, the start-up time (t2) is not affected by the input voltage. Figure 13 shows the output voltage start-up using different soft-start capacitance values. It is mandatory a minimum capacitor value of 22nF. The pin 2 cannot be left open. Figure 11a. Timing Diagram in Inhibit, overcurrent and turn off condition Figure 11b. Start up sequence.
INHIBIT V SS/INH
1.8V 1.3V 1.2V
OVER-CURRENT
TURN-OFF
VCC UVLO ON t VSS/INH
t IC
ILIM IO ILIM
1.8V
t PWM
t1 IC
t
t
PWM
VO
t
t
VO
V CC UVLO OFF
D97IN811
t
t2
D97IN812
t
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AN1061 APPLICATION NOTE
Feedback disconnection In case of feedback disconnection, the duty cycle increases versus the max allowed value bringing the output voltage close to the input supply. This condition could destroy the load. To avoid this dangerous condition, the device is forcing a little current(1.4A typical) out of the pin 8 (E/A Feedback). If the feedback is disconnected, open loop, and the impedance at pin 8 is higher than 3.5M Ohm, the voltage at this pin goes higher than the internal reference voltage located on the non-inverting error amplifier input , and turns-off the power device. Figure 12. Soft start time(t2) vs Vo and Css
tss (ms) 70
1F
Figure 13. Output rising voltage with Css 56nF, 100nF, 220nF.
D97IN687
60 50 40
470nF
30
330nF
20
220nF
10
100nF
0
0
3
6
9
12 15 18 21 24
VO(V)
Zero load In normal operation, the output regulation is also guaranteed because the bootstrap capacitor is recharged, cycle by cycle, by means of the energy flowing into the chocke. Under light load conditions, this topology tends to operate in burst mode, with random repetition rate of the bursts. An internal new function makes this device capable of keeping the output voltage in full regulation with 1mA of load current only. Between 1mA and 500A, the output is kept in regulation up to 8% above the nominal value. Here the circuitry providing the control : * 1- a comparator located on the bootstrap section is sensing the bootstrap voltage; when this is lower than 5V, the internal power VDMOS is forced ON for one cycle and OFF for the next.. * 2- during this operation mode, i.e. 500A of load current, the E/A control is lost. To avoid output overvoltages, a comparator with one input connected to pin 8, and the second input connected to a threshold 8% higher that nominal output, turns OFF the internal power device the output is reaching that threshold. When the output current, or rather, the current flowing into the choke, is lower than 500A, that is also the consumption of the bootstrap section, the output voltage starts to increase, approaching the supply voltage. Output Overvoltage Protection (OVP) The output overvoltage protection, OVP, is realised by using an internal comparator, which input is connected to pin 8, the feedback, that turns-off the power stage when the OVP threshold is reached. This threshold is typically 8% higher than the feedback voltage. When a voltage divider is requested for adjusting the output voltage, the OVP intervention will be set at: Vovp = 1.08 Vfb (Ra+Rb)/Rb where Ra is the resistor connected to the output. Power Stage
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AN1061 APPLICATION NOTE
The power stage is realised by a N-channel D-mos transistor with a Vdss in excess of 60V and typ. Rdson of 290mOhm (measured at the device pins). To minimise the Rdson, means also to minimise the conduction losses. But also the switching losses have to be taken into consideration, mainly for the two following reasons: a- they are affecting the system efficiency and the device power dissipation b- because they generate EMI. TURN - ON At turn-on of the power element, or better, the rise time of the current(di/dt) at turn-on is the most critical parameter to compromise. At a first approach, it looks that the faster it is the rise time and the lower are the turn-on losses. It's not completely true. There is a limit, and it's introduce by the recovery time of the recirculation diode. Above this limit, about 100A/usec, only drawbacks are obtained: 1- turn-on overcurrent is decreasing efficiency and system reliability 2- big EMI encreasing. The L4978 has been developed with a special focus on this dynamic area. An innovative and proprietary gate driver, with two different timings, has been introduced. When the diode reverse voltage is reaching about 3V, the gate is sourced with low current (see Figure14) to assure the complete recovery of the diode without generating unwanted extra peak currents and noise. After this threshold, the gate drive current is quickly increased, producing a fast rise time till the peak current, so maintaining the efficiency very high. TURN - OFF The turn-off behaviour, is shown at Figure14. Figure 15 shows the details of the internal power stage and driver, where at Q2 is demanded the turnoff of the power switch, S. TYPICAL APPLICATION Figure 16 shows the typical application circuit, where the input supply voltage, Vcc, can range from 8 to 55V operating, and the output voltage adjustable from 3.3V to 40V. The selected components, and in particular input and output capacitors, are able to sustain the device voltage ratings, and the corresponding RMS currents. Electrical Specification Input Voltage range 8V-55V Output Voltage 5.1V 3% (Line, Load and Temperature) Output ripple 34mV Output Current range 1mA-2A Max Output Ripple current 20% Iomax Current limit 3A Switching frequency 100kHz Target Efficiency 85%@2A Vin = 55V 92%@0.5A Vin = 12V
Main components description
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AN1061 APPLICATION NOTE
Figure 14. Turn on and Turn off (pin 2, 3)
Turn On
Turn Of f
Figure 15. Power stage internal circuit.
CSS Vi
Q3 I1 I2
Q1
S Q2 SRS
CSS
L +
Q4
Q5
from PWM LATCH
D
C
VO -
I4
I5
I3
DELAY
D97IN659
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AN1061 APPLICATION NOTE
INPUT CAPACITOR The input capacitors have to be able to support the max input operating voltage of the device and the max rms input current. Figure 16. Application Circuit
Vin=8V to 55V 5 R1 20K 3 C1 220F 63V C7 220nF C2 2.7nF 2 7 8
L4978
4 1 6 L1 126H (77120) D1 GI SB560 C8 330F
V O=5.1V/2A
R3
C5 100nF
R2 9.1K C4 22nF
C6 100nF
R4
D98IN915
C1=220F/63V EKE C2=2.7nF C5=100nF C6=100nF C7=220nF/63V C8=330F/35V CG Sanyo L1=126H KoolMu 77120 - 55 Turns - 0.5mm R1=20K R2=9.1K D1=GI SB560
L4978
VO (V) 3.3 5.1 12 15 18 24 R3(K) 0 2.7 12 16 20 30 4.7 4.7 4.7 4.7 4.7 R4(K)
The input current is squared and the quality of these capacitors has to be very high to minimise its Figure 17. Efficiency vs Output Current [% ] power dissipation generated by the internal ESR, 95 improving the system reliability. Moreover, input caV cc = 8V pacitors are also affecting the system efficiency. V c c =12 V 90 The max Irms current flowing through the input capacitors is:
85
2 where is the expected system efficiency, D is the duty cycle and Io the output dc current. This function reaches the maximum value at D = 0.5 and the equivalent rms current is equal to Io/2. The following diagram is the graphical representation of the above equation, with an estimated efficiency of 85% at different output currents. The maximum and minimum duty cycles are:
Dmax =
Irms = Io
D - +
2 D2
V c c =24V
D2
80
75
V c c =48V
70
fs w = 100k H z V o=5 .1V
65
60
0
0 . 2 0 .4 0 .6 0 .8
1 1 .2 1 .4 1 .6 1 .8 Io [A ]
2
2 .2
Vo + Vf = 0.66 Vi n min + Vf Vo + Vf = 0.1 Vin max + Vf
Dmin =
where Vf is the freewheeling diode forward voltage.
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AN1061 APPLICATION NOTE
This formula is not taking into account the power mos Rdson, considering negligible the inherent voltage drop, respect input and output voltages. At full load, 2A and D = 0.5% the rms capacitor current to be sustained is of 1A. The selected EKE 220F/63V Roderstain is able to support this current. Figure 18. Input Capacitance rms current vs duty cycle
IRMS
IO=2A
D98IN916
Inductor Selection The inductor ripple current is fixed at 20% of Iomax and is 0.4A, the inductor needed is: L = (Vo + Vf) (1 - Dmin) = 126H (eq1) Io fsw
1 0.8 0.6
I O=1A IO=1.5A
IO=1.2A
0.4
IO=0.5A
0.2 0 0.1 0.2 0.3 0.4
IO=0.2A
0.5
0.6
0.7 0.8
D
The L Io2 is 0.53 and the size core chose is 77120 (125) Magnetics KoolM material. At full load the magnetising force is about 25 Oersted, so, in order to compensate a 30% reduction of inductance due to the DC current level, they are wiring 55 turns, which corresponds to 213H of inductance at light load. It is possible to graficate the Eq 1 as a function of Vo and Vinmax at 100kHz and 200kHz (see Figure 19a-b).
These curves are useful to define the inductor value immediately. -core losses Core losses are proportional to the magnetic flux swing into the core material. To evaluate the flux swing is used the following formula: L Io = 477Gauss B = No Ale 10-4 where Ale is the core cross section [m2]. The choosen core material family has an empirical equation to calculate the losses:
Figure 19a. Inductor needed as a function of maximum input voltage and output voltage at fsw=100kHz
LO (H)
VCCmax=
Figure 19b. Inductor needed as a function of maximum input voltage and output voltage at fsw=200kHz
LO (H)
VCCmax=
D98IN917
D98IN918
250 200 150
40V
250 200 150
35V
100
30V 24V 18V
100
40 V
15V
50 0
50
24
35V
30
15 V
V
V
18 V
0
4
8
12 16 20 24 28 32
VO(V)
0
0
4
8
12 16 20 24 28 32
VO(V)
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AN1061 APPLICATION NOTE
Pl = B2 fsw1.5 Vl = 180mW Where Vl is the core volume in cm3, B is expressed in KGauss and fsw in KHz. The core increasing temperature is: Pl T = 13.6 where Pl is expressed in mW. Output Capacitor The selection of Cout is driven by the output ripple voltage required, 1% of Vo. This is defined by the output capacitance ESR and with the maximum ripple current (0.4A) the maximum ESR is: ESR= Vo/Io = 0.051/0.4=127.5m The selected capacitance is 330F/35V CG Sanyo with ESR = 86m and the ripple voltage is 0.67% of Vo (34mV). The drop due to a fast load variation of 1A produce an output drop of : ESR Io = 86mV that is the 1.6% of the output voltage. Output capacitance has to support a load transient until the inductor current reaches the increased current. The output drop during an output current variation is: Vo = (Io)2 Lo 2 Co (Vinmin Dmax - Vo) Eq(2)
0.833
= 8.5C
Figure 20. Output drop (%) vs minimum input voltage
VO *100 VO (%) 5 4 3
D98IN919
Where Io is the current load variation (0.5A to 2A), Dmax is the maximum duty cycle (0.95), Vo is 5.1V and Lo is 126H . Equation 2, normalised by Vo is represented in the following diagram( Figure 20) as a function of the minimum input voltage. These curves are represented for different output capacitor 220F, 330F, 2x330F. Compensation Network The complete control loop block diagram is shown in Figure 21 The transfer functions described are: Error amplifier and compensation block
2 1 0 8
33
2 x3
220F
0
F
30
F
12 16 20 24 28 32 36 40 Vinmin(V)
A(s) =
Avo (1 + s Rc Cc) s Ro Co Rc Cc + s (Ro Cc + Ro Co + Rc Cc) + 1
2
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AN1061 APPLICATION NOTE
Co is the parallel between the output capacitance and the external capacitance of the Error Amplifier Rc and Cc are the compensation values Figure 21. Block diagram compensation loop
V REF + VO
A(s)
Vc/Vct
LC
D97IN697
LC filter 1 + Resr Cout s Resr L L Cout (1 + ) s2 + (Resr Cout+ ) s + 1 RL RL PWM gain Vcc Vcc 6 6 = Vct Vcc - 1 where Vct is the peak to peak sawtooth oscillator. Voltage divider Ao(s) = Figure 22. Error Amplifier Compensation Circuit
Cc gm Ro Rc Co
Avo=gm*Ro
D97IN698
=
R4 R3 + R4
The Error Amplifier basic characteristics are: Ro = 1.2M Figure 23. Output Filter Avo = 57dB
L Cout Resr Iout=2A
CO = 220pF The poles and zeros value are: Fo = 1 1 = = 5.6KHz 2 Resr Cout 2 0.086 330 10-6
RL
D98IN925
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AN1061 APPLICATION NOTE
Fp =
1 1 = = 780Hz L Cout 2 2 126 10-6 330 10-6 1 1 = = 795Hz 2 Rc Cc 2 9.1 103 22 10-9
Focomp =
Fp1 =
1 1 = = 6.032Hz 2 Ro Cc 2 1.2 106 22 10-9 1 1 = = 80KHz 2 Rc Co 2 9.1 103 220 10-12
Fp2 =
The compensation is realised choosing the Focomp nearly the frequency of the double pole due to the LC filter. Using compensation network R1 = 9.1K, C6 = 22nF and C5 = 220pF obtain the Gain and Phase Bode plot of Figures 24-25. Is possible to omit C5 because does not influence the system stability but is useful only to reduce the noise. The cut off frequency and a phase margin are: Fc = 3.7KHz; Phase margin = 21
APPLICATION IDEAS Compensation of voltage drop along the wires. For supplying a remote load, without using sensing wires, the below application shows how to compensate the voltage drop along the wires. If Rz is the total resistance of the line, fixing the resistor Rk (see Figure 1), to a value given by the below formula : Figure 25. Phase Bode open loop plot
D98IN920
Figure 24. Gain Bode open loop plot
Fa (dB) 60 50 40 30 20 10 0 -10 -20 1 16/19 10 100 1K 10K f(Hz)
Fa () -20 -40 -60 -80 -100 -120 -140 -160 -180 1 10 100 1K
D98IN921
10K
f(Hz)
AN1061 APPLICATION NOTE
Rk = R2 the regulated load voltage, VL , is : VL = Rz Iq + (R1 + R2) 1 Rz , R1 Vref
R2
where Vref is the feedback voltage reference of 3.3V and Iq is the device quiescent current (typ. 2.5mA). The Cadd capacitor has to be chosen so that the frequency, given by 1/[2Cadd*R1R2/(R1+R2)], is around two decades below the switching frequency.
It follows a table for Rk choice with, for example, a line resistance, Rz=0.5Ohm :
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AN1061 APPLICATION NOTE
Figure 27. Compensation of Voltage Drop along the Wires
BOOT Vcc
100nF
Iload
VL>3.3V
20k OSC
OUT
126uH (77120) GI SB560 68nF R1 Rz+jwLz RL 100uF VOUT VL
L4978
FB
68nF 220uF Vs
22uF 2.7nF SS- INH 100nF GND Iq 9.1K COMP 22nF R2
Rk
D98IN923
Table for RK choice
Vload(V) 5.1 12 24 R1() 2.43K 12.1K 28.7K R2() 4.7K 4.7K 4.7K Rk() 0.97 0.19 0.08
Figure 28. Output Voltage vs. Output Current
V (V)
D98IN924
Vout
Rz Iout
VL
0
1
2 Iout [A]
3
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AN1061 APPLICATION NOTE
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Price & Availability of AN1061

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